Electrostatic discharge protection circuit and display device applying the same

ABSTRACT

This application relates to an electrostatic discharge (ESD) protection circuit, includes: a first switch, electrically coupled to a first node through a control end, electrically coupled to a ground node through a first end, and electrically coupled to a signal input node through a second end; a capacitor electrically coupled between the first node and the signal input node; a second switch, electrically coupled to a low level line through a control end and a first end, and electrically coupled to the signal input node through a second end; and a third switch, electrically coupled to a high level line through a control end, and electrically coupled to the first node through a first end, being electrically coupled to the low level line through a second end.

BACKGROUND Technical Field

This application relates to an electrostatic discharge (ESD) protectioncircuit and a display device using the ESD protection circuit, and inparticular, to an ESD protection circuit composed of a plurality ofswitch components and a display device using the ESD protection circuit.

Related Art

Electrostatic (charge) is a positive or negative charge formed on anobject surface by charge imbalance due to some reasons. ElectrostaticDischarge (ESD) occurs when the charge is transferred and differentpotentials discharge mutually. When the electrostatic voltage is 2000 V,the human body cannot feel it. However, electrostatic sensitivecomponents used in our production may be damaged by it, because a CMOSintegrated circuit device can only withstand a voltage of 250 V to 2000V, and would cause damage once the voltage is exceeded. ESD may causebreakdown of an integrated circuit chip medium, fusing of core wires,accelerated aging of leakage currents, change of electrical performanceparameters and so on.

Currently, a LCD panel circuit has a relatively serious ESD phenomenon,and it is very common that circuits are damaged by ESD. To prevent ESDfrom damaging internal lines or components of a LCD panel, especiallyfor active switches (Thin film transistor, TFT), an ESD protectioncircuit is generally designed on the LCD panel. When an ESD voltage ispresent on a pixel array, an ESD protection circuit made beside thepixel array has to be capable of switching on early to discharge ESDcurrents. Therefore, components used in the ESD protection circuit haveto have a relatively low breakdown voltage or a relatively high turn-onspeed.

In terms of a-Si, whether it is in a full N-type active switch (NTFT) ora full P-type active switch (PTFT) process, the gate and the drain ofthe active switch are usually connected, i.e., an equivalent diodeassembly can be formed. Two equivalent diode assemblies form a group,two ends are respectively electrically coupled to a high level line(VGH) and a low level line (VGL), and a node connected to the twoassemblies is then connected to a signal circuit or a power circuit, tothus form an ESD protection circuit. When high-voltage staticelectricity enters the signal circuit or the power circuit, there wouldbe a group of forward or reverse equivalent diode assembliescorresponding to the high-voltage static electricity whether thehigh-voltage static electricity is a positive voltage or a negativevoltage, to discharge the positive voltage or the negative voltagethrough the unilateral connection characteristic of diodes.

However, the high level line and the low level line are generally thin,such that lines connected to upper and lower ends of the equivalentdiode assemblies would form relatively great equivalent resistancerespectively. Therefore, a discharge current may be relatively small,not being conducive to ESD.

SUMMARY

To resolve the foregoing technical problem, this application is aimed atproviding an ESD protection circuit, to increase a discharge path toincrease the rate of ESD.

The objective of this application and the solution to the technicalproblem thereof are implemented through the following technicalsolution. An ESD protection circuit according to this applicationincludes: a first switch, electrically coupled to a first node through acontrol end of the first switch, electrically coupled to a ground nodethrough a first end of the first switch, and electrically coupled to asignal input node through a second end of the first switch; a capacitorelectrically coupled between the first node and the signal input node; asecond switch, electrically coupled to a first level line through acontrol end and a first end of the second switch, and electricallycoupled to the signal input node through a second end of the secondswitch; and the third switch, electrically coupled to a second levelline through a control end of the third switch, and electrically coupledto the first node through a first end of the third switch, andelectrically coupled to the first level line through a second end of thethird switch; wherein the signal input node obtained a staticelectricity, a potential of the static electricity is incompatible witha potential of the second level line, the capacitor is voltage-regulateddue to the static electricity to adjust a potential of the first node,to open the first switch and the third switch, and the staticelectricity passes through the first switch and the third switch todischarge towards the ground node and the first level line.

This application may further resolve the technical problem thereofthrough the following technical measures.

In an embodiment of this application, the first switch, the secondswitch and the third switch are N-type transistors, the first level lineis a low level line, and the second level line is a high level line.

In an embodiment of this application, the potential of the first node isequal to that of the low level line, and the first switch is turned off.

In an embodiment of this application, the signal input node getspositive-potential static electricity, and when the potential of thepositive-potential static electricity is a potential between the highlevel line and the low level line, the first switch and the third switchare turned off.

In an embodiment of this application, the first switch, the secondswitch and the third switch are P-type transistors, the first level lineis a high level line, and the second level line is a low level line.

In an embodiment of this application, the potential of the first node isequal to that of the high level line, and the first switch is turnedoff.

In an embodiment of this application, the signal input node getsnegative-potential static electricity, and when the potential of thenegative-potential static electricity is a potential between the highlevel line and the low level line, the first switch and the third switchare turned off.

In an embodiment of this application, when the potential of the staticelectricity is a potential between the second level line and the firstlevel line, the capacitor forms an open circuit to down-regulate thepotential of the first node.

A second objective of this application is an ESD protection circuit,including: a first switch, electrically coupled to a first node througha control end of the first switch, and electrically coupled to a groundnode through a first end of the first switch, and electrically coupledto a signal input node through a second end of the first switch; acapacitor electrically coupled between the first node and the signalinput node; a second switch, electrically coupled to a first level linethrough a control end and a first end of the second switch, andelectrically coupled to the signal input node through a second end ofthe second switch; and a third switch, electrically coupled to a secondlevel line through a control end of the third switch, and electricallycoupled to the first node through a first end of the third switch, andelectrically coupled to the first level line through a second end of thethird switch; wherein the signal input node obtained a staticelectricity, the potential of the static electricity is incompatiblewith a potential of the second level line, the capacitor isvoltage-regulated due to the static electricity to up-regulate apotential of the first node, to open the first switch and the thirdswitch to make the first node electrically coupled to the first levelline, and the static electricity passes through the first switch and thethird switch to discharge towards the ground node and the first levelline; when the potential of the static electricity is a potentialbetween the first level line and the second level line, the capacitorforms an open circuit to down-regulate the potential of the first node,to turn off the first switch and the third switch; the ground node iselectrically coupled to a ground wire or a common voltage wire; andoperating currents of the first switch and the second switch are below 1μA.

Another objective of this application is a display panel, including adisplay panel; and the ESD protection circuit having the technicalfeatures in any of the above embodiments.

This application increases a discharge path to increase the rate of ESDand the electric quantity, avoiding that ESD causes damage to internallines or components of a LCD panel. The improvement to the circuit iseasy to implement, and also helps enhance reliability of the circuit. Itis applicable to making of panels of various sizes, and theapplicability is relatively high.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a schematic diagram of an exemplary ESD protection circuit;

FIG. 1b is a schematic diagram of an exemplary ESD protection circuit;

FIG. 1c is a schematic diagram of a theoretical equivalent circuit of anexemplary ESD protection circuit;

FIG. 1d is a schematic diagram of an actual equivalent circuit of anexemplary ESD protection circuit;

FIG. 2a is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit;

FIG. 2b is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit;

FIG. 3a is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit; and

FIG. 3b is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit.

DETAILED DESCRIPTION

The following embodiments are described with reference to theaccompanying drawings, which are used to exemplify specific embodimentsfor implementation of this application. Terms about directions mentionedin this application, such as “on”, “below”, “front”, “back”, “left”,“right”, “in”, “out”, and “side surface” merely refer to directions inthe accompanying drawings. Therefore, the used terms about directionsare used to describe and understand this application, and are notintended to limit this application.

The accompanying drawings and the description are considered to beessentially exemplary, rather than limitative. In the figures, unitswith similar structures are represented by using the same referencenumber. In addition, for understanding and ease of description, the sizeand the thickness of each component shown in the accompanying drawingsare arbitrarily shown, but this application is not limited thereto.

In the accompanying drawings, for clarity and ease of understanding anddescription, components are enlarged. It should be understood that whena component is described to be “on” “another component”, the componentmay be directly on another component, or there may be an intermediatecomponent.

In addition, throughout this specification, unless otherwise explicitlydescribed to have an opposite meaning, the word “include” is understoodas including the component, but not excluding any other component. Inaddition, throughout the specification, “on” means that one is locatedabove or below a target component and does not necessarily mean that oneis located on the top based on a gravity direction.

To further describe the technical measures taken in this application toachieve the intended invention objective and effects thereof, specificimplementations, structures, features, and effects of an ESD protectioncircuit and a display panel applying the same that are providedaccording to this application are described below in detail withreference to the drawings and preferred embodiments.

The display panel of this application may include an active array (TFT)substrate and a color filter (CF) substrate.

In some embodiments, the display panel of this application may be acurved display panel.

In some embodiments, the active array (TFT) and the color filter (CF) ofthis application may be formed on the same substrate.

FIG. 1a is a schematic diagram of an exemplary ESD protection circuit.Referring to FIG. 1a , an ESD protection circuit includes a first switchT10 and a second switch T20, which are both N-type active switches(NTFT). A first end T11 of the first switch T10 is a drain (D), a secondend T12 of the first switch T10 is a source (S), and a control end T13of the first switch T10 is a gate (G). A first end T21 of the secondswitch T20 is a drain (D), a second end T22 of the second switch T20 isa source (S), and a control end T23 of the second switch T20 is a gate(G). The control end T13 and the first end T11 of the first switch T10are connected, and the control end T23 and the first end T21 of thesecond switch T20 are connected. The second end T12 of the first switchT10 is electrically coupled to a high level line VGH, the first end T21of the second switch T20 is electrically coupled to a low level lineVGL, and a node connected to the first switch T10 and the second switchT20 is further connected to a signal input connection point P, to thusform an ESD protection circuit.

FIG. 1b is a schematic diagram of an exemplary ESD protection circuit.Referring to FIG. 1b , an ESD protection circuit includes a first switchT10 and a second switch T20, which are both P-type active switches(NTFT). A first end T11 of the first switch T10 is a drain (D), a secondend T12 of the first switch T10 is a source (S), and a control end T13of the first switch T10 is a gate (G). A first end T21 of the secondswitch T20 is a drain (D), a second end T22 of the second switch T20 isa source (S), and a control end T23 of the second switch T20 is a gate(G). The control end T13 and the first end T11 of the first switch T10are connected, and the control end T23 and the first end T21 of thesecond switch T20 are connected. The first end T11 of the first switchT10 is electrically coupled to a high level line VGH, the second end T22of the second switch T20 is electrically coupled to a low level lineVGL, and a node connected to the first switch T10 and the second switchT20 is further connected to a signal input connection point P, to thusform an ESD protection circuit.

FIG. 1c is a schematic diagram of a theoretical equivalent circuit of anexemplary ESD protection circuit, which is a schematic diagram of atheoretical equivalent circuit of the ESD protection circuits shown inFIG. 1a and FIG. 1b . In terms of a-Si, in a full N-type active switch(NTFT) process, the gate and the grain of the N-type active switch aregenerally connected, i.e., an equivalent diode assembly can be formed.Therefore, after the control end T13 and the first end T11 of the firstswitch T10 are connected and the control end T23 and the first end T21of the second switch T20 are connected, the first switch T10 and thesecond switch T20 form an equivalent diode assembly respectively. Twoequivalent diode assemblies form a group, two ends thereof arerespectively electrically coupled to a high level line VGH and a lowlevel line VGL, and a node connected to the two assemblies is thenconnected to a signal input connection point P. In terms of a-Si, in afull P-type active switch (PTFT) process, the gate and the grain of theP-type active switch are generally connected, i.e., an equivalent diodeassembly can be formed. Therefore, after the control end T13 and thefirst end T11 of the first switch T10 are connected and the control endT23 and the first end T21 of the second switch T20 are connected, thefirst switch T10 and the second switch T20 form an equivalent diodeassembly respectively. Two equivalent diode assemblies form a group, twoends thereof are respectively electrically coupled to a high level lineVGH and a low level line VGL, and a node connected to the two assembliesis then connected to a signal input connection point P.

When high-voltage static electricity enters the signal input connectionpoint P, there would be a group of forward or reverse equivalent diodeassemblies corresponding to the high-voltage static electricity whetherthe high-voltage static electricity is a positive voltage or a negativevoltage. Based on the unilateral connection characteristic of diodes,positive and negative charges of the high-voltage static electricity canrapidly discharge to the high level line and the low level line, todischarge the positive voltage or the negative voltage.

FIG. 1d is a schematic diagram of an actual equivalent circuit of anexemplary ESD protection circuit, which is a schematic diagram of anactual equivalent circuit of the ESD protection circuits shown in FIG.1a and FIG. 1b . As shown in FIG. 1c , line widths of the high levelline VGH and the low level line VGL are generally fine; therefore, aline at the second end T12 of the first switch T10 and a line at thefirst end T21 of the second switch T20 may generate equivalent resistors(R1, R2) with relatively great resistance, and the electrostatic currentI1 or I2 relative to discharge is relatively small.

FIG. 2a is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit.Referring to FIG. 2a , an ESD protection circuit 300 includes: a firstswitch T10, electrically coupled to a first node A through a control endT13 of the first switch T10, electrically coupled to a ground node GNDthrough a first end T11 of the first switch T10, and electricallycoupled to a signal input node P through a second end T12 of the firstswitch T10; a capacitor C electrically coupled between the first node Aand the signal input node P; a second switch T20, electrically coupledto a first level line through a control end T23 and a first end T21 ofthe second switch T20, and electrically coupled to the signal input nodeP a second end T22 of the second switch T20; and a third switch T30,electrically coupled to a second level line through a control end T33 ofthe third switch T30, and electrically coupled to the first node Athrough a first end T31 of the third switch T30, and electricallycoupled to the first level line through a second end T32 of the thirdswitch T30; wherein the signal input node P obtained a staticelectricity, the potential of the static electricity is incompatiblewith a potential of the second level line, the capacitor C isvoltage-regulated due to the static electricity to adjust a potential ofthe first node A, to open the first switch T10 and the third switch T30,and the static electricity passes through the first switch T10 and thethird switch T30 to discharge towards the ground node GND and the firstlevel line.

In some embodiments, the ground node GND is electrically coupled to aground wire or a common voltage wire.

In some embodiments, the signal input node P is electrically coupled toa line transmitting signals or power. The line includes a data line, agate line, a gamma line, a reference voltage line (Vref Line), asequential control line (CK Line), an enabled line (OE Line) and otheridentical, related and similar lines, but is not limited thereto. Linescapable of transmitting signals or power are applicable thereto.

In some embodiments, when the potential of the static electricity is apotential between the second level line and the first level line, thecapacitor forms an open circuit to down-regulate the potential of thefirst node.

In some embodiments, the first switch T10, the second switch T20 and thethird switch T30 are depleted transistors.

In some embodiments, the first end T11 of the first switch T10 is adrain (D), the second end T12 of the first switch T10 is a source (S),and the control end T13 of the first switch T10 is a gate (G); the firstend T21 of the second switch T20 is a drain (D), the second end T22 ofthe second switch T20 is a source (S), and the control end T23 of thesecond switch T20 is a gate (G); the first end T31 of the third switchT30 is a drain (D), the second end T32 of the third switch T30 is asource (S), and the control end T33 of the third switch T30 is a gate(G).

FIG. 2b is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit, which isa schematic diagram of an actual equivalent circuit of the ESDprotection circuit shown in FIG. 2 a.

In an embodiment of this application, the first switch T10, the secondswitch T20 and the third switch T30 are N-type transistors, the firstlevel line is a low level line VGL, and the second level line is a highlevel line VGH.

As stated above, line widths of the high level line VGH and the lowlevel line VGL are generally fine; therefore, a line at the first endT11 of the first switch T10 and a line at the first end T21 of thesecond switch T20 may generate equivalent resistors with relativelygreat resistance. In this example, a first equivalent resistor R1′ isformed between the first switch T10 and the ground node GND, and asecond equivalent resistor R2′ is formed between the second switch T20and the low level line VGL.

In some embodiments, the signal input node gets positive-potentialstatic electricity, and the potential of the positive-potential staticelectricity is higher than that of the high level line VGH. Thecapacitor C is affected by the positive-potential static electricity. Incombination with special effects of capacity coupling, the cross-voltageof the capacitor C is improved, thereby improving the potential of thefirst node A, to open the first switch T10. However, the drain (D) ofthe first switch T10, i.e., the first end T11, is connected to theground node GND, for example, a ground wire (GND) or a common voltagewire (Vcom). Generally, the line width of the ground wire or the commonvoltage wire is much greater than the line width of the low level lineVGL. Therefore, R1′ may be smaller than R1, and the generated currentI1′ is also greater than the original I1. Secondly, the potential of thefirst node A is improved, which would turn on the third switch T30,thereby generating a current I3, to form another ESD path. Therefore,through the third switch T30, the positive-potential static electricityintroduced by the signal input node P can discharge to the low levelline VGL. Therefore, the magnitude of current that an electrostatic pathcan discharge is the sum of the current I1′ and the current I3. Thetotal magnitude of discharge current is much more than the current I1,and thus there is a better protection effect on the static electricity.

In some embodiments, when the positive-potential static electricitydischarges, the potential of the first node A may be gradually reduced.Once the potential of the first node A is equal to that of the low levelline VGL, the first switch T10 is turned off.

In some embodiments, the capacitor C may be considered as an opencircuit in a direct current, and has characteristics of blocking DC,making AC through, making high frequencies through and blocking lowfrequencies. Therefore, when the potential of the positive-potentialstatic electricity got by the signal input node P is a potential betweenthe high level line VGH and the low level line VGL, the first switch T10and the third switch T30 are turned off, and the capacitor C is an opencircuit in the circuit.

FIG. 3a is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit.Referring to FIG. 3a , an ESD protection circuit 300 includes: a firstswitch T10, electrically coupled to a first node A through a control endT13 of the first switch T10, and electrically coupled to a ground nodeGND through a first end T11 of the first switch T10, and electricallycoupled to a signal input node P through a second end T12 of the firstswitch T10; a capacitor C electrically coupled between the first node Aand the signal input node P; a second switch T20, electrically coupledto a first level line through a control end T23 and a first end T21 ofthe second switch T20, and electrically coupled to the signal input nodeP through a second end T22 of the second switch T20; and a third switchT30, electrically coupled to a second level line through a control endT33 of the third switch T30, and electrically coupled to the first nodeA through a first end T31 of the third switch T30, and electricallycoupled to the first level line through a second end T32 of the thirdswitch T30.

In some embodiments, the first switch T10, the second switch T20 and thethird switch T30 are P-type transistors, the first level line is a highlevel line VGH, and the second level line is a low level line VGL.

In some embodiments, the first end T11 of the first switch T10 is adrain (D), the second end T12 of the first switch T10 is a source (S),and the control end T13 of the first switch T10 is a gate (G); the firstend T21 of the second switch T20 is a drain (D), the second end T22 ofthe second switch T20 is a source (S), and the control end T23 of thesecond switch T20 is a gate (G); the first end T31 of the third switchT30 is a drain (D), the second end T32 of the third switch T30 is asource (S), and the control end T33 of the third switch T30 is a gate(G).

FIG. 3b is a schematic diagram of application of a method according toan embodiment of this application to an ESD protection circuit, which isa schematic diagram of an actual equivalent circuit of the ESDprotection circuit shown in FIG. 2a . As stated above, line widths ofthe high level line VGH and the low level line VGL are generally fine;therefore, a line at the first end T21 of the second switch T20 and aline at the first end T11 of the first switch T10 may generateequivalent resistors with relatively great resistance. In this example,a first equivalent resistor R1′ is formed between the second switch T20and the low level line VGL, and a second equivalent resistor R2′ isformed between the first switch T10 and the ground node GND.

In some embodiments, the signal input node P gets negative-potentialstatic electricity, and the potential of the negative-potential staticelectricity is lower than that of the low level line VGL. The capacitorC is affected by the negative-potential static electricity. Incombination with special effects of capacity coupling, the cross-voltageof the capacitor C is reduced, thereby reducing the potential of thefirst node A, to open the first switch T10. However, the drain (D) ofthe first switch T10, i.e., the first end T11, is connected to theground node GND, for example, a ground wire (GND) or a common voltagewire (Vcom). Generally, the line width of the ground wire or the commonvoltage wire is much greater than the line width of the low level lineVGL. Therefore, R2′ may be smaller than R2, and the generated currentI2′ is also greater than the original I2. Secondly, the potential of thefirst node A is reduced, which would turn on the third switch T30,thereby generating a current I3, to form another ESD path. Therefore,through the third switch T30, the negative-potential static electricityintroduced by the signal input node P can discharge to the high levelline VGH. Therefore, the magnitude of current that an electrostatic pathcan discharge is the sum of the current I2′ and the current I3. Thetotal magnitude of discharge current is much more than the current I2,and thus there is a better protection effect on the static electricity.

In some embodiments, when the negative-potential static electricitydischarges, the potential of the first node A may be graduallyincreased. Once the potential of the first node A is equal to that ofthe high level line VGL, the first switch T10 is turned off.

In some embodiments, the capacitor C may be considered as an opencircuit in a direct current, and has characteristics of blocking DC,making AC through, making high frequencies through and blocking lowfrequencies. Therefore, when the potential of the negative-potentialstatic electricity got by the signal input node P is a potential betweenthe high level line VGH and the low level line VGL, the first switch T10and the third switch T30 are turned off, and the capacitor C is an opencircuit in the circuit.

In an embodiment of this application, an ESD protection circuit of thisapplication includes: a first switch T10, electrically coupled to afirst node A through a control end T13 of the first switch T10,electrically coupled to a ground node GND through a first end T11 of thefirst switch T10, and electrically coupled to a signal input node Pthrough a second end T12 of the first switch T10; a capacitor Celectrically coupled between the first node A and the signal input nodeP; a second switch T20, electrically coupled to a first level linethrough a control end T23 and a first end T21 of the second switch T20,and electrically coupled to the signal input node P through a second endT22 of the second switch T20; and a third switch T30, electricallycoupled to a second level line through a control end T33 of the thirdswitch T30, a first end T31 of the third switch T30 being electricallycoupled to the first node A, and a second end T32 of the third switchT30 being electrically coupled to the first level line; wherein thesignal input node P obtained a static electricity, the potential of thestatic electricity is incompatible with a potential of the second levelline, the capacitor C is voltage-regulated due to the static electricityto adjust a potential of the first node A, to open the first switch T10and the third switch T30, and the static electricity passes through thefirst switch T10 and the third switch T30 to discharge towards theground node GND and the first level line, and operating currents of thefirst switch T10 and the second switch T20 are below 1 μA.

In an embodiment of this application, a display device of thisapplication includes a control module, a display panel, and the ESDprotection circuit having the technical features of any of the foregoingembodiments. The control module provides a control signal and a powersignal. When a driving circuit of the display panel receives suchsignals, necessary data and power are transmitted to a display area,such that the display panel obtains power and signals presenting imagedemands. The ESD protection circuit 300 includes: a first switch T10,electrically coupled to a first node A through a control end T13 of thefirst switch T10, and electrically coupled to a ground node GND througha first end T11 of the first switch T10, and electrically coupled to asignal input node P through a second end T12 of the first switch T10; acapacitor C electrically coupled between the first node A and the signalinput node P; a second switch T20, electrically coupled to a first levelline through a control end T23 and a first end T21 of the second switchT20, and electrically coupled to the signal input node P through asecond end T22 of the second switch T20; and a third switch T30,electrically coupled to a second level line through a control end T33 ofthe third switch T30, and electrically coupled to the first node Athrough a first end T31 of the third switch T30, and a second end T32 ofthe third switch T30 being electrically coupled to the first level linethrough a second end T32 of the third switch T30; wherein potentials ofthe first level line and the second level line connected to the ESDprotection circuit 300 is controlled through the control module; theground node GND is electrically coupled to a ground wire or a commonvoltage wire; the display panel includes a first panel and a secondpanel disposed oppositely, and the ESD protection circuit 300 may bedisposed in at least one of the first panel and the second panel.

This application increases a discharge path to increase the rate of ESDand the electric quantity, avoiding that ESD causes damage to internallines or components of a LCD panel. The improvement to the circuit iseasy to implement, and also helps enhance reliability of the circuit. Itis applicable to making of panels of various sizes, and theapplicability is relatively high.

The wordings such as “in some embodiments” and “in various embodiments”are repeatedly used. The wordings usually refer to differentembodiments, but they may also refer to a same embodiment. The words,such as “comprise”, “have”, and “include”, are synonyms, unless othermeanings are indicated in the context thereof.

The foregoing descriptions are merely preferred embodiments of thisapplication, and are not intended to limit this application in any form.Although this application has been disclosed above through the preferredembodiments, the embodiments are not intended to limit this application.Any person skilled in the art can make some variations or modifications,which are equivalent changes, according to the foregoing disclosedtechnical content to obtain equivalent embodiments without departingfrom the scope of the technical solutions of this application. Anysimple amendment, equivalent change, or modification made to theforegoing embodiments according to the technical essence of thisapplication without departing from the content of the technicalsolutions of this application shall fall within the scope of thetechnical solutions of this application.

What is claimed is:
 1. An electrostatic discharge (ESD) protectioncircuit, comprising: a first switch, electrically coupled to a firstnode through a control end of the first switch, and electrically coupledto a ground node through a first end of the first switch, andelectrically coupled to a signal input node through a second end of thefirst switch; a capacitor electrically coupled between the first nodeand the signal input node; a second switch, electrically coupled to afirst level line through a control end and a first end of the secondswitch, and electrically coupled to the signal input node through asecond end of the second switch; and a third switch, electricallycoupled to a second level line through a control end of the thirdswitch, and electrically coupled to the first node through a first endof the third switch, and electrically coupled to the first level linethrough a second end of the third switch; wherein when staticelectricity having a voltage potential that is greater in magnitude thanthe voltage potential of the second level line is presented on thesignal input node, the capacitor adjusts the voltage potential of thefirst node to turn on the first switch and the third switch, wherein thestatic electricity then discharges through the first switch towards theground node and discharges through the third switch towards the firstlevel line.
 2. The ESD protection circuit according to claim 1, whereinthe first switch, the second switch and the third switch are N-typetransistors, the first level line is a low level line, and the secondlevel line is a high level line.
 3. The ESD protection circuit accordingto claim 2, wherein the potential of the first node is equal to that ofthe low level line, and the first switch is turned off.
 4. The ESDprotection circuit according to claim 2, wherein the signal input nodegets positive-potential static electricity, and when the potential ofthe positive-potential static electricity is a potential between thehigh level line and the low level line, the first switch and the thirdswitch are turned off.
 5. The ESD protection circuit according to claim1, wherein the first switch, the second switch and the third switch areP-type transistors, the first level line is a high level line, and thesecond level line is a low level line.
 6. The ESD protection circuitaccording to claim 5, wherein the potential of the first node is equalto that of the high level line, and the first switch is turned off. 7.The ESD protection circuit according to claim 5, wherein the signalinput node gets negative-potential static electricity, and when thepotential of the negative-potential static electricity is a potentialbetween the high level line and the low level line, the first switch andthe third switch are turned off.
 8. The ESD protection circuit accordingto claim 1, wherein when the potential of the static electricity is apotential between the second level line and the first level line, thecapacitor forms an open circuit to down-regulate the potential of thefirst node.
 9. The ESD protection circuit according to claim 1, whereinoperating currents of the first switch and the second switch are below 1μA.
 10. An electrostatic discharge (ESD) protection circuit, comprising:a first switch, electrically coupled to a first node through a controlend of the first switch, and electrically coupled to a ground nodethrough a first end of the first switch, and electrically coupled to asignal input node through a second end of the first switch; a capacitorelectrically coupled between the first node and the signal input node; asecond switch, electrically coupled to a first level line through acontrol end and a first end of the second switch, and electricallycoupled to the signal input node through a second end of the secondswitch; and a third switch, electrically coupled to a second level linethrough a control end of the third switch, and electrically coupled tothe first node through a first end of the third switch, and electricallycoupled to the first level line through a second end of the thirdswitch; wherein when static electricity having a voltage potential thatis greater in magnitude than the voltage potential of the second levelline is presented on the signal input node, the capacitor adjusts thevoltage potential of the first node to turn on the first switch and thethird switch, wherein the static electricity then discharges through thefirst switch towards the ground node and discharges through the thirdswitch towards the first level line; when the voltage potential of thestatic electricity is a voltage potential between the first level lineand the second level line, the capacitor forms an open circuit todown-regulate the voltage potential of the first node, to turn off thefirst switch and the third switch; the ground node is electricallycoupled to a ground wire or a common voltage wire; and operatingcurrents of the first switch and the second switch are below 1 μA.
 11. Adisplay device, comprising: a display panel; and an electrostaticdischarge (ESD) protection circuit, comprising: a first switch,electrically coupled to a first node through a control end of the firstswitch, and electrically coupled to a ground node through a first end ofthe first switch, and electrically coupled to a signal input nodethrough a second end of the first switch; a capacitor electricallycoupled between the first node and the signal input node; a secondswitch, electrically coupled to a first level line through a control endand a first end of the second switch, and electrically coupled to thesignal input node through a second end of the second switch; and a thirdswitch, electrically coupled to a second level line through a controlend of the third switch, and electrically coupled to the first nodethrough a first end of the third switch, and electrically coupled to thefirst level line through a second end of the third switch; wherein whenstatic electricity having a voltage potential that is greater inmagnitude than the voltage potential of the second level line ispresented on the signal input node, the capacitor adjusts the voltagepotential of the first node to turn on the first switch and the thirdswitch, wherein the static electricity then discharges through the firstswitch towards the ground node and discharges through the third switchtowards the first level line.
 12. The display device according to claim11, wherein the first switch, the second switch and the third switch areN-type transistors, the first level line is a low level line, and thesecond level line is a high level line.
 13. The display device accordingto claim 12, wherein the potential of the first node is equal to that ofthe low level line, and the first switch is turned off.
 14. The displaydevice according to claim 12, wherein the signal input node getspositive-potential static electricity, and when the potential of thepositive-potential static electricity is a potential between the highlevel line and the low level line, the first switch and the third switchare turned off.
 15. The display device according to claim 11, whereinthe first switch, the second switch and the third switch are P-typetransistors, the first level line is a high level line, and the secondlevel line is a low level line.
 16. The display device according toclaim 15, wherein the potential of the first node is equal to that ofthe high level line, and the first switch is turned off.
 17. The displaydevice according to claim 15, wherein the signal input node getsnegative-potential static electricity, and when the potential of thenegative-potential static electricity is a potential between the highlevel line and the low level line, the first switch and the third switchare turned off.
 18. The display device according to claim 11, whereinwhen the potential of the static electricity is a potential between thesecond level line and the first level line, the capacitor forms an opencircuit to down-regulate the potential of the first node.
 19. Thedisplay device according to claim 11, wherein the ground node iselectrically coupled to a ground wire or a common voltage wire.
 20. Thedisplay device according to claim 11, wherein operating currents of thefirst switch and the second switch are below 1 μA.